1. Field of the Invention
The present invention relates to a photosensor and a photosensor array, and more particularly to a photosensor array using a thick amorphous silicon film which is a light-dependent variable resistor element, as a photosensor element.
2. Description of the Related Art
Ones of the present inventors have filed Japanese Patent Application entitled photosensor using an amorphous silicon (a-Si) film and photosensor array as a photosensor element (Japanese Patent Application No. 2009-162612). The amorphous silicon (a-Si) film of the photosensor in the invention disclosed in the filed Japanese Patent Application operates as the light-dependent variable resistance element in which a resistance is varied in response to an incident light.
FIG. 13 is a circuit diagram illustrating a circuit configuration of a photosensor array in the invention disclosed in the filed Japanese Patent Application.
In the photosensor array according to the invention disclosed in the filed Japanese Patent Application, a dashed frame A of FIG. 13 represents a photosensor pixel. The photosensor pixel includes three transistors MT1 to MT3, a light-dependent variable resistance element AS1, a capacitive element (storage capacitor) C1, a gate line GCLK for conducting read reset, a reset line SVRS that applies a reset voltage VRS, bias lines SVB1, SVB2, SVAB, that apply bias voltages (fixed potential) VB1,VB2,VAB respectively and a signal output line OUT.
FIG. 13 illustrates a photosensor array in which the number of photosensor pixels is m×K. FIG. 13 illustrates a specific circuit diagram of the photosensor having four pixels of n to (n+1) rows and J to (J+1) columns.
At a lower side of the periphery of the photosensor array, reset transistors MTR each for resetting a voltage at a signal output line OUT, a reset line SVRST for applying a reset voltage VRST, and a terminal that inputs a control voltage RSTPLS for controlling output bonding pads PAD and the reset transistors MTR are arranged. A shift register 12 is disposed at a left side of the periphery of the photosensor array.
FIG. 14 is a diagram illustrating a configuration of the light-dependent variable resistance element AS1 illustrated in FIG. 13. The light-dependent variable resistance element AS1 illustrated in FIG. 14 includes an upper electrode 92, a lower electrode 94, and amorphous silicon (a-Si) 93 held between the upper electrode and the lower electrode 94. FIG. 14 illustrates the light-dependent variable resistance element AS1 and the capacitive element C1. FIG. 15 illustrates an equivalent circuit of the light-dependent variable resistance element AS1 illustrated in FIG. 14.
FIG. 16 is a timing chart illustrating the operation of the photosensor array illustrated in FIG. 13. Hereinafter, the operation of the photosensor pixel indicated in the dashed frame A in FIG. 13 will be described with reference to FIG. 16.
For facilitation of description, it is assumed that bias voltages are VB1=VB2=0V (GND), VAB=10V, and the reset voltages are VRS=5V, and VRST=0V. Also, the voltages of respective clocks (φ1, φ2) are 10V in high level (hereinafter, referred to as H level) or 0V in low level (hereinafter, referred to as L level). The voltage values of the respective bias voltages are exemplary, and may be voltages other than the above-described values. Also, the bias voltage VAB may be a voltage of the reset voltage VRS or higher.
Referring to FIG. 13, the respective rows of the photosensor pixels are sequentially scanned downward in FIG. 13 by the shift register 12. That is, referring to FIG. 13, the gate lines GCLK are sequentially applied with on-voltage pulses in the increasing order of number.
First, when a voltage of 10V which is H level is applied to a gate line GCLK (n+1) by the shift register 12, the transistor MT1 turns on in the photosensor pixel, and an internal node N1 of the photosensor pixel is electrically rendered conductive to the bias line SVRS, and a voltage at the internal node N1 becomes 5V that is the same potential as that of the bias voltage VRS.
Subsequently, when a voltage that is applied to the gate line GCLK (n+1) becomes a voltage of 0V which is L level, the internal node N1 of the photosensor pixel becomes an electrically isolated node, but a voltage at the internal node N1 is held by the capacitive element C1 between the bias line SVB2 and the node N1.
In this state, the internal node N1 is connected to the bias line SVB1 applied with the bias potential VB1 of 0V. For example, a resistance value of the light-dependent variable resistance element AS1 is set to a value at which a dark current of about several tens fA flows at a room temperature.
When the light-dependent variable resistance element AS1 is irradiated with light (infrared rays), a resistance is decreased by carrier pairs generated in semiconductor by photoelectric conversion. The light is detected by the aid of this phenomenon. The photosensor for an environmental purpose is designed, for example, so that a current of a few pA flows in the light-dependent variable resistance element AS1.
In this way, electric charges stored in the internal node N1 are discharged to the bias line SVB2 through the light-dependent variable resistance element AS1. The amount of discharged electric charges fluctuates due to the resistance of the light-dependent variable resistance element AS1 in the dark state, and the amount of incident light. Accordingly, the voltage at the node N1 after a given time has been elapsed is different according to the amount of incident light.
A storage time of an optical signal due to the incident light is from the time when a voltage of 0V that is L level is applied to the gate line GCLK(n+1) by the shift register 12 until the gate line scanning by the shift register 12 substantially goes round (after one frame) and then a voltage of 10V that is H level is applied to the gate line GCLK(n).
At a time t2, when the control voltage RSTPLS becomes, for example, a voltage of 10V that is H level, the reset transistor MTR illustrated in FIG. 13 becomes on, and a signal output line OUT(j) is reset to the reset voltage VRST of 0V.
At a time t3, when the control voltage RSTPLS becomes 0V (L level), the signal output line OUT(j) becomes in a floating state.
At a time t4, when a voltage of 10V that is H level is applied to the gate line GCLK (n), the transistor MT3 turns on, and the output line OUT(j) and the bias line SVAB are connected to each other through the transistor MT2 and the transistor MT3.
A gate voltage of the transistor MT3 is 10V, and the transistor MT3 operates in an unsaturated state, but the transistor MT2 operates in a saturated state. This is because a gate of the transistor MT2 is the internal node N1, and becomes 5V or lower in response to the amount of incident light as described above.
Accordingly, the transistor MT2 is cut off by a source voltage (V3) corresponding to the gate voltage. For that reason, a voltage at the output line OUT(1) becomes a value corresponding to the voltage at the internal node N1, as a result of which an output voltage corresponding to the amount of incident light is obtained.
At a time t5, when a voltage of 0V which is L level is applied to the gate line GCLK(n), the transistor MT3 turns off.
At a time t8, when a voltage of 10V that is H level is applied to the gate line GCLK(n+1), the transistor MT1 turns on, and the internal node N1 is reset to the bias voltage VRS of 5V.
The above operation is repeated in each of the pixels.